The present invention relates to an insulated gate field effect transistor and a tuning circuit.
LC tuned circuits are widely used in RF circuits, such as oscillators and tuned amplifiers. It is often necessary, for instance in multiband radio equipment, to change the resonant frequency of a circuit. At HF frequencies, relays can be used to switch capacitors, inductors or entire tuned circuits into and out of use. However, at higher frequencies, relays become unsuitable. Furthermore, relays have a relatively high current demand and are undesirable at any frequency for this reason.
Subsequently, PIN diodes came to be used for RF switching, including the switching of capacitors and inductors into and out of tuned circuits. However, in order for a PIN diode switch to close, the PIN diode must be forward biased which results in a significant current flow.
The use of MOSFETs to effect switched tuning has the advantage of negligible current demand and has been proposed in Kral, A. et al, xe2x80x9cRF-CMOS Oscillators with Switched Tuningxe2x80x9d, Proceedings of the Custom Integrated Circuits Conference, pp 555-558, 1998, Kuhn, W. et al., xe2x80x9cA 200 MHz CMOS Q-Enhanced LC Bandpass Filterxe2x80x9d, IEEE Journal of Solid-state Circuits, Vol. 31, no. 8, pp 1112-1122, August 1996 and Cho, T. et al., xe2x80x9cA Single-Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread-Spectrum Digital Cordless Phonesxe2x80x9d, Proceedings of the IEEE International Solid-State Circuits Conference, pp 228-229 and 464, 1999. However, the use of MOSFETs in this way has not become commonplace.
Furthermore, the known circuits are restricted to switching components in an out of circuit by controlling the resistance between a node, e.g. one terminal of a capacitor, and an AC ground, typically 0V for NMOS devices and +V for PMOS devices.
According to the present invention, there is provided a tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal, the first reactance being connected between the source of the field effect transistor and a first node and the second reactance having the same value as the first reactance and being connected between the drain of the field effect transistor and a second node, wherein the first and second nodes are arranged so as to experience a balanced ac signal. The field effect transistor may be a p- or n-channel device and is preferably an enhancement mode device. A balanced ac signal comprises two waveforms which are reciprocal relative to an ac ground, such as is found in a balanced transmission line.
The first and second reactances may be both either capacitors or inductors.
A capacitor and/or an inductor may be connected between said nodes.
According to the present invention, there is also provided an insulated gate field effect transistor comprising source and drain regions with a surrounding region and gate electrode means provided over a channel or channels between said source and drain region and over at least part of the boundary between said source and drain regions and said surrounding region, said surrounding region being provided with ground connection means for connection to an AC ground. The source and drain regions are preferably n- or n+-type within a p-type substrate region. If, however, the source and drain regions are p- or p+-type, the substrate region may be an n-type region within a greater p-type region. If the source and drain regions are n+-type the surrounding region is n- or n+-type and if the source and drain regions are p- or p+-type the surrounding region is p- or p+-type. The normalised substrate resistance of PMOS devices can be much lower than that for NMOS devices. Accordingly, when sized correctly PMOS devices can perform better that NMOS devices for switching tuning components.
The ground connection means is distinct from and in addition to the conventional substrate connection found in insulated gate field effect devices.
Preferably, the ground connection means comprises a plurality of interconnected ohmic contacts to said substrate region.
Preferably, the gate electrode means encompasses said source and drain regions.
The source and drain regions may be in a finger structure arrangement. Preferably, however, the source and drain regions are in a waffle structure arrangement.
Providing metallic interconnections between the sources and metallic interconnections between the drain regions and between the source regions of small insulated gate field effect transistor having multi-drain/multi-source topographies, e.g. the waffle structure.
Preferably, therefore the insulated gate field effect transistor includes a plurality of source and drain regions and an interconnection layer in which said source regions are connected together and said drain regions are connected together, the conductors of the interconnection layer being connected to said source and drain regions by splaying conductive paths. Splaying the connections in this way increases the spacing between the points which need to be interconnected in interconnection layer.
Preferably, said source and drain regions are in a waffle structure arrangement. More preferably, the interconnection layer comprises a source interconnection structure and a drain interconnection structure, said structures comprising respective sets of fingers extending diagonally, with respect to said waffle structure arrangement, which ate interdigitated.
An insulated gate field effect transistor according to the present invention may be advantageously employed in a circuit according to the present invention.
A circuit according to the present invention may be employed in a resonant circuit such as an oscillator or a filter.
According to the present invention, there is further provided an insulated gate field effect transistor comprising a plurality of source and drain regions and an interconnection layer in which said source regions are connected together and said drain regions are connected together, the conductor or conductors of the interconnection layer being connected to said source and drain regions by splaying conductive paths.
Preferably, said source and drain regions are in a waffle structure arrangement. More preferably, the interconnection layer comprises a source interconnection structure and a drain interconnection structure, said structures comprising respective sets of fingers extending diagonally, with respect to said waffle structure arrangement, which are interdigitated.